Compiler-Directed Dynamic Voltage Scaling Based on Program Regions

This paper discusses the design and implementation of the first compiler that optimizes programs for power and energy using dynamic voltage scaling. The compiler identifies program regions where the CPU can be slowed down without resulting in a significant overall performance loss. For such regions the lowest CPU voltage is selected that operates correctly under the reduced clock frequency. Our trace-based compiler prototype uses the SUIF2 compiler infrastructure. For the SPECfp95 benchmark, simulation results show energy savings of up to 24% with performance penalties of less than 2.7%.